Instanciación de Artix 7 Block RAM en Vivado 2015.2

Ok, estoy tratando de crear una instancia de Block RAM en un verdadero tipo de puerto dual. He usado el catálogo de IP y el generador de memoria de bloque en Vivado, lo que me ha dado un archivo gigante que ahora necesito reducir a las partes que necesito. Esta es la primera vez que uso ram de bloque interno o ram. Mi pregunta es qué necesito del primer código para que funcione en Vivado. La segunda parte del código es con lo que he estado trabajando, lo que me dio muchos errores que publiqué en otro hilo que encontré en la red de controladores múltiples.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;

ENTITY blk_mem_gen_0 IS
   PORT (
      clka : IN STD_LOGIC;
      rsta : IN STD_LOGIC;
      ena : IN STD_LOGIC;
        wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
       addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
       dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
       douta : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
       clkb : IN STD_LOGIC;
       rstb : IN STD_LOGIC;
      enb : IN STD_LOGIC;
          web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
          dinb : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
       doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
        );
       END blk_mem_gen_0;

       ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
        ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
        ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch:                                            

       COMPONENT blk_mem_gen_v8_2 IS
       GENERIC (
       C_FAMILY : STRING;
       C_XDEVICEFAMILY : STRING;
      C_ELABORATION_DIR : STRING;
       C_INTERFACE_TYPE : INTEGER;
       C_AXI_TYPE : INTEGER;
       C_AXI_SLAVE_TYPE : INTEGER;
       C_USE_BRAM_BLOCK : INTEGER;
      C_ENABLE_32BIT_ADDRESS : INTEGER;
     C_CTRL_ECC_ALGO : STRING;
      C_HAS_AXI_ID : INTEGER;
      C_AXI_ID_WIDTH : INTEGER;
      C_MEM_TYPE : INTEGER;
      C_BYTE_SIZE : INTEGER;
      C_ALGORITHM : INTEGER;
      C_PRIM_TYPE : INTEGER;
      C_LOAD_INIT_FILE : INTEGER;
     C_INIT_FILE_NAME : STRING;
      C_INIT_FILE : STRING;
     C_USE_DEFAULT_DATA : INTEGER;
      C_DEFAULT_DATA : STRING;
      C_HAS_RSTA : INTEGER;
     C_RST_PRIORITY_A : STRING;
     C_RSTRAM_A : INTEGER;
  C_INITA_VAL : STRING;
  C_HAS_ENA : INTEGER;
  C_HAS_REGCEA : INTEGER;
  C_USE_BYTE_WEA : INTEGER;
  C_WEA_WIDTH : INTEGER;
  C_WRITE_MODE_A : STRING;
  C_WRITE_WIDTH_A : INTEGER;
  C_READ_WIDTH_A : INTEGER;
  C_WRITE_DEPTH_A : INTEGER;
  C_READ_DEPTH_A : INTEGER;
  C_ADDRA_WIDTH : INTEGER;
  C_HAS_RSTB : INTEGER;
  C_RST_PRIORITY_B : STRING;
  C_RSTRAM_B : INTEGER;
  C_INITB_VAL : STRING;
  C_HAS_ENB : INTEGER;
  C_HAS_REGCEB : INTEGER;
  C_USE_BYTE_WEB : INTEGER;
  C_WEB_WIDTH : INTEGER;
  C_WRITE_MODE_B : STRING;
  C_WRITE_WIDTH_B : INTEGER;
  C_READ_WIDTH_B : INTEGER;
  C_WRITE_DEPTH_B : INTEGER;
  C_READ_DEPTH_B : INTEGER;
  C_ADDRB_WIDTH : INTEGER;
  C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
  C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
  C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
  C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
  C_MUX_PIPELINE_STAGES : INTEGER;
  C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
  C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
  C_USE_SOFTECC : INTEGER;
  C_USE_ECC : INTEGER;
  C_EN_ECC_PIPE : INTEGER;
  C_HAS_INJECTERR : INTEGER;
  C_SIM_COLLISION_CHECK : STRING;
  C_COMMON_CLK : INTEGER;
  C_DISABLE_WARN_BHV_COLL : INTEGER;
  C_EN_SLEEP_PIN : INTEGER;
  C_USE_URAM : INTEGER;
  C_EN_RDADDRA_CHG : INTEGER;
  C_EN_RDADDRB_CHG : INTEGER;
  C_EN_DEEPSLEEP_PIN : INTEGER;
  C_EN_SHUTDOWN_PIN : INTEGER;
  C_DISABLE_WARN_BHV_RANGE : INTEGER;
  C_COUNT_36K_BRAM : STRING;
  C_COUNT_18K_BRAM : STRING;
  C_EST_POWER_SUMMARY : STRING
  );
   PORT (
      clka : IN STD_LOGIC;
      rsta : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      regcea : IN STD_LOGIC;
      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
      dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
      douta : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
      clkb : IN STD_LOGIC;
      rstb : IN STD_LOGIC;
      enb : IN STD_LOGIC;
      regceb : IN STD_LOGIC;
      web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
      addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
      dinb : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
       doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
      injectsbiterr : IN STD_LOGIC;
       injectdbiterr : IN STD_LOGIC;
       eccpipece : IN STD_LOGIC;
       sbiterr : OUT STD_LOGIC;
       dbiterr : OUT STD_LOGIC;
        rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
       sleep : IN STD_LOGIC;
      deepsleep : IN STD_LOGIC;
         shutdown : IN STD_LOGIC;
       s_aclk : IN STD_LOGIC;
  s_aresetn : IN STD_LOGIC;
  s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
  s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
  s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
  s_axi_awvalid : IN STD_LOGIC;
  s_axi_awready : OUT STD_LOGIC;
  s_axi_wdata : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
  s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
  s_axi_wlast : IN STD_LOGIC;
  s_axi_wvalid : IN STD_LOGIC;
  s_axi_wready : OUT STD_LOGIC;
  s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
  s_axi_bvalid : OUT STD_LOGIC;
  s_axi_bready : IN STD_LOGIC;
  s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
  s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
  s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
  s_axi_arvalid : IN STD_LOGIC;
  s_axi_arready : OUT STD_LOGIC;
  s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  s_axi_rdata : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
  s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
  s_axi_rlast : OUT STD_LOGIC;
  s_axi_rvalid : OUT STD_LOGIC;
  s_axi_rready : IN STD_LOGIC;
  s_axi_injectsbiterr : IN STD_LOGIC;
  s_axi_injectdbiterr : IN STD_LOGIC;
  s_axi_sbiterr : OUT STD_LOGIC;
  s_axi_dbiterr : OUT STD_LOGIC;
  s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
   );
   END COMPONENT blk_mem_gen_v8_2;

   ATTRIBUTE X_CORE_INFO : STRING;
   ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_                                                                                                  
     ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
    ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS      
    ATTRIBUTE CORE_GENERATION_INFO : STRING;
   ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS            
   ATTRIBUTE X_INTERFACE_INFO : STRING;
   ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS  ce:bram:1.0 BRAM_PORTA   ;
   ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS ace:bram:1.0 BRAM_PORTA ;
   ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS 
   ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS 
  ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS 
  ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS  
  ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS 
  ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS 
  ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS  
  ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS  
  ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS  
  ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS  
 ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS  
 ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS 
BEGIN
   U0 : blk_mem_gen_v8_2
GENERIC MAP (
  C_FAMILY => "artix7",
  C_XDEVICEFAMILY => "artix7",
  C_ELABORATION_DIR => "./",
  C_INTERFACE_TYPE => 0,
  C_AXI_TYPE => 1,
  C_AXI_SLAVE_TYPE => 0,
  C_USE_BRAM_BLOCK => 0,
  C_ENABLE_32BIT_ADDRESS => 0,
  C_CTRL_ECC_ALGO => "NONE",
  C_HAS_AXI_ID => 0,
  C_AXI_ID_WIDTH => 4,
  C_MEM_TYPE => 2,
  C_BYTE_SIZE => 9,
  C_ALGORITHM => 1,
  C_PRIM_TYPE => 1,
  C_LOAD_INIT_FILE => 0,
  C_INIT_FILE_NAME => "no_coe_file_loaded",
  C_INIT_FILE => "blk_mem_gen_0.mem",
  C_USE_DEFAULT_DATA => 0,
  C_DEFAULT_DATA => "0",
  C_HAS_RSTA => 1,
  C_RST_PRIORITY_A => "CE",
  C_RSTRAM_A => 0,
  C_INITA_VAL => "0",
  C_HAS_ENA => 1,
  C_HAS_REGCEA => 0,
  C_USE_BYTE_WEA => 0,
  C_WEA_WIDTH => 1,
  C_WRITE_MODE_A => "WRITE_FIRST",
  C_WRITE_WIDTH_A => 18,
  C_READ_WIDTH_A => 18,
  C_WRITE_DEPTH_A => 1024,
  C_READ_DEPTH_A => 1024,
  C_ADDRA_WIDTH => 10,
  C_HAS_RSTB => 1,
  C_RST_PRIORITY_B => "CE",
  C_RSTRAM_B => 0,
  C_INITB_VAL => "0",
  C_HAS_ENB => 1,
  C_HAS_REGCEB => 0,
  C_USE_BYTE_WEB => 0,
  C_WEB_WIDTH => 1,
  C_WRITE_MODE_B => "WRITE_FIRST",
  C_WRITE_WIDTH_B => 18,
  C_READ_WIDTH_B => 18,
  C_WRITE_DEPTH_B => 1024,
  C_READ_DEPTH_B => 1024,
  C_ADDRB_WIDTH => 10,
  C_HAS_MEM_OUTPUT_REGS_A => 0,
  C_HAS_MEM_OUTPUT_REGS_B => 0,
  C_HAS_MUX_OUTPUT_REGS_A => 0,
  C_HAS_MUX_OUTPUT_REGS_B => 0,
  C_MUX_PIPELINE_STAGES => 0,
  C_HAS_SOFTECC_INPUT_REGS_A => 0,
  C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
  C_USE_SOFTECC => 0,
  C_USE_ECC => 0,
  C_EN_ECC_PIPE => 0,
  C_HAS_INJECTERR => 0,
  C_SIM_COLLISION_CHECK => "ALL",
  C_COMMON_CLK => 0,
  C_DISABLE_WARN_BHV_COLL => 0,
  C_EN_SLEEP_PIN => 0,
  C_USE_URAM => 0,
  C_EN_RDADDRA_CHG => 0,
  C_EN_RDADDRB_CHG => 0,
  C_EN_DEEPSLEEP_PIN => 0,
  C_EN_SHUTDOWN_PIN => 0,
  C_DISABLE_WARN_BHV_RANGE => 0,
  C_COUNT_36K_BRAM => "0",
  C_COUNT_18K_BRAM => "1",
  C_EST_POWER_SUMMARY => "Estimated Power for IP     :     3.1193 mW"
)
enter code here
PORT MAP (
  clka => clka,
  rsta => rsta,
  ena => ena,
  regcea => '0',
  wea => wea,
  addra => addra,
  dina => dina,
  douta => douta,
  clkb => clkb,
  rstb => rstb,
  enb => enb,
  regceb => '0',
  web => web,
  addrb => addrb,
  dinb => dinb,
  doutb => doutb,
  injectsbiterr => '0',
  injectdbiterr => '0',
  eccpipece => '0',
  sleep => '0',
  deepsleep => '0',
  shutdown => '0',
  s_aclk => '0',
  s_aresetn => '0',
  s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
  s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
  s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
  s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
  s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
  s_axi_awvalid => '0',
  s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
  s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
  s_axi_wlast => '0',
  s_axi_wvalid => '0',
  s_axi_bready => '0',
  s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
  s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
  s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
  s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
  s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
  s_axi_arvalid => '0',
  s_axi_rready => '0',
  s_axi_injectsbiterr => '0',
  s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;

enter code here

La siguiente paz de código que me dieron para trabajar. Esta paz de código me da errores encontrados en la red de múltiples controladores. También fue escrito para un chip Spartan 3. Necesito uno para un chip artix 7. Gracias

   RAMB16_S18_S18_inst : RAMB16_S18_S18
   generic map (
      INIT_A => X"00000", --  Value of output RAM registers on Port A at up
    INIT_B => X"00000", --  Value of output RAM registers on Port B at startup
  SRVAL_A => X"00000", --  Port A ouput value upon SSR assertion
  SRVAL_B => X"00000", --  Port B ouput value upon SSR assertion
  WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
  WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
  SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL
  -- The follosing INIT_xx declarations specify the intiial contents of the RAM
  -- Address 0 to 255
  INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_0F =>                X"0000000000000000000000000000000000000000000000000000000000000000",
  -- Address 256 to 511
  INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
  -- Address 512 to 767
  INIT_20 => X"00000000000000004703CEC28D8100282E2E8037903190319031903100000000",
  INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
  -- Address 768 to 1023
  INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
  INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
  -- The next set of INITP_xx are for the parity bits
  -- Address 0 to 255
  INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
  -- Address 256 to 511
  INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
  -- Address 512 to 767
  INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
  -- Address 768 to 1023
  INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
  INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")


port map (
  DOA => DOA,      -- Port A 16-bit Data Output
  DOB => dataout,      -- Port B 16-bit Data Output
  DOPA => DOPA,    -- Port A 2-bit Parity Output
  DOPB => DOPB,    -- Port B 2-bit Parity Output
  ADDRA => ADDRA,  -- Port A 10-bit Address Input
  ADDRB => addr,  -- Port B 10-bit Address Input
  CLKA => CLKA,    -- Port A Clock
  CLKB => ram_clk,    -- Port B Clock
  DIA => DIA,      -- Port A 16-bit Data Input
  DIB => datain,      -- Port B 16-bit Data Input
  DIPA => DIPA,    -- Port A 2-bit parity Input
  DIPB => DIPB,    -- Port-B 2-bit parity Input
  ENA => ENA,      -- Port A RAM Enable Input
  ENB => ram_enable,      -- PortB RAM Enable Input
  SSRA => '0',    -- Port A Synchronous Set/Reset Input
  SSRB => ram_reset,    -- Port B Synchronous Set/Reset Input
  WEA => WEA,      -- Port A Write Enable Input
  WEB => we       -- Port B Write Enable Input
 );
No necesita un núcleo IP BlockRAM para generar una RAM de doble puerto. Es posible usar alrededor de 20 líneas de código VHDL genéricas. Consulte la guía Vivado HDL para ver ejemplos de uso.
He usado un código de ejemplo de este documento Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs UG768 (v14.7) 2 de octubre de 2013

Respuestas (1)

El uso de un fragmento de código VHDL genérico es mucho más pequeño....

Ejemplo: PoC.mem.ocrom.tdp

entity ocram_tdp is
    generic (
        A_BITS      : positive;
        D_BITS      : positive
    );
    port (
        clk1 : in   std_logic;
        clk2 : in   std_logic;
        ce1 : in    std_logic;
        ce2 : in    std_logic;
        we1 : in    std_logic;
        we2 : in    std_logic;
        a1   : in   unsigned(A_BITS-1 downto 0);
        a2   : in   unsigned(A_BITS-1 downto 0);
        d1   : in   std_logic_vector(D_BITS-1 downto 0);
        d2   : in   std_logic_vector(D_BITS-1 downto 0);
        q1   : out std_logic_vector(D_BITS-1 downto 0);
        q2   : out std_logic_vector(D_BITS-1 downto 0)
    );
end entity;


architecture rtl of ocram_tdp is
    constant DEPTH : positive := 2**A_BITS;
        signal ram          : ram_t;
        signal a1_reg       : unsigned(A_BITS-1 downto 0);
        signal a2_reg       : unsigned(A_BITS-1 downto 0);
begin
        process (clk1, clk2)
        begin   -- process
            if rising_edge(clk1) then
                if ce1 = '1' then
                    if we1 = '1' then
                        ram(to_integer(a1)) <= d1;
                    end if;
                    a1_reg <= a1;
                end if;
            end if;
            if rising_edge(clk2) then
                if ce2 = '1' then
                    if we2 = '1' then
                        ram(to_integer(a2)) <= d2;
                    end if;
                    a2_reg <= a2;
                end if;
            end if;
        end process;
        q1 <= ram(to_integer(a1_reg));      -- returns new data
        q2 <= ram(to_integer(a2_reg));      -- returns new data
end architecture;

Consulte el archivo vinculado para obtener más funciones:

  • leer el contenido de RAM del disco en el momento de la síntesis
  • cambiar a las primitivas de Altera si se sintetiza con Quartus-II
Necesito usar el block ram interno porque estoy leyendo y escribiendo en el block ram con el código vhdl y leyendo y escribiendo desde el block ram con código C.
Síntesis de la guía del usuario de Vivado Design Suite (UG901, página 94 Técnicas de codificación de RAM HDL. Si tiene un inicio de sesión de Xilinx, hay un enlace para descargar ejemplos de HDL (VHDL y Verilog). Los ejemplos en UG901 muestran, entre otras cosas, cómo inferir bloques de RAM.
Este código se asigna a BlockRAM. Es por eso que se llama RAM en chip (ocram).
OK. Todavía necesito la parte de creación de instancias, ¿verdad?
O lo copia processen su archivo...
Gracias por la ayuda, tendré que investigar más y leer. ¿No te estoy siguiendo cuando dices agregar procesarlo a tu archivo?
Instanciación de Artix 7 Block RAM en Vivado 2015.2
RespuestasAquíPolítica de privacidad1y, 0v